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r/RISCV

21,577 subscribers
RISC-V (pronounced "risk-five") is a license-free, modular, extensible computer instruction set architecture (ISA).

Originally designed for computer architecture research at Berkeley, RISC-V is now used in everything from $0.10 CH32V003 microcontroller chips to the pan-European supercomputing initiative, with 64 core 2 GHz workstations in between.

RISC-V is suitable for custom silicon chips, as a soft core in an FPGA, or as a high performance software Virtual Machine.

riscv.org

Notice: This subreddit is not actively monitored, so the posts here are only a small subset of what exists on reddit.

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Hardware Help wanted Information
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to r/RISCV by ntn8888
5 months ago
Milk-V Duo: Where's the default dts file used by the kernel for board?
Help wanted
to r/RISCV by keithreid-sfw
4 months ago
LaTeX runs fine in the DevTerm R-01
Information
to r/RISCV by keithreid-sfw
4 months ago
RISC-V Assembly projects
Help wanted
to r/RISCV by testus_maximus
8 months ago
Preview thumbnail for issue tracking/discussion/documentation for Android on RISC-V image
issue tracking/discussion/documentation for Android on RISC-V
to r/RISCV by testus_maximus
8 months ago
The Past, Present and Future of RISC-V
to r/RISCV by jinnyjuice
1 month ago
What kind of kernels are in the works? What seems to be the 'best practice' and/or 'most popular' at the moment?
to r/RISCV by ntn8888
1 year ago
google suspends listing to resale cheap boards...
to r/RISCV by ntn8888
1 year ago
XT-ZB1 development board BL702 RISC-V SOC shipped from US
to r/RISCV by ntn8888
1 year ago
Preview thumbnail for lash dt-bl10 (risc-v) board, using openocd image
lash dt-bl10 (risc-v) board, using openocd
to r/RISCV by icoinformation2021
8 months ago
Goodbye x86. The FUTURE is RISC-V