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Adc for SDR
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So I've been looking into designing the hardware for my own SDR. I've noticed that some of the ADCs have a sampling rate which is slower than the maximum input signal. For example I saw one ADC which had a sampling rate of 2.2gsps and said it could read read signals up to 2.5GHz. How is it possible to make such a claim? You can't matain the integrity of a signal if you aren't even sampling one time per cycle can you?
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