I am an idiot newbie who is working his way through Pong Chu's "FPGA Prototyping by VHDL Example". I've read the first 6 chapters, and have decided I know enough to be dangerous and have written what I think is an upcounter:

http://pastebin.com/RC9NY9NJ

You can see from the code that I use the en port(?) from the entity declaration as part of an "and" construct, to decide if the counter should be incremented. It's line 22 of the pastebin file: elsif( rising_edge(clk) and en ) then upctr_reg <= upctr_next;

My question is: Is this a bad idea?

Intuitively, I expect the VHDL synthesizer to simply create an AND gate with en as one of the inputs. The output of said AND gate then getting wired to the clk input to all the FFs that store the bits of the register. Which all seems fine to me.

Since nothing will happen until the clock edge anyway (by design), I don't see the point in running the process when en changes. That's why I don't want to put it on the sensitivity list. Something in my brain is saying: "en is a level-sensitive input, not an edge-sensitive one. Nothing changes when en goes high (or low), things only change at the clock edge."

Is my understanding of all this correct?

(Probably a lot of people are saying to themselves: "Why didn't he just try it?" Two reasons: One, I'm still waiting for the #@$#@^%$&* Xilinx ISE download to finish. Two, even if it does work I'd still like to know if this is considered "bad style" or something like that.)