Hi Everyone,

I have just started learning VHDL by working with Grant Searle's Multicomp design based on a Cyclone II mini dev board: http://zx80.netai.net/grant/Multicomp/index.html

Having got the basics sorted, I am now trying to modify Grant's 6502 Multicomp VHDL model to use a 16K ROM HEX file (Commodore PET V2). The EP2C5 Cyclone II device does not have enough internal memory to create a 16K ROM device so I am trying to understand how I could bootstrap the HEX file - ie: preload it into the attached 32K SRAM.

Am I right in thinking that having defined the connectivity for external RAM (which is working, as per Grant's design), I need to create some form of one-shot loop to read the ROM data from an array and send it to the external RAM and also implement a lock to make this happen before the design resets the synthesized processor and jumps to its reset vector?

My 'net searches turn up lots of info about simulating ROM inside the FPGA using Quartus and the Megawizard tool, but I am drawing a blank on bootstrapping external RAM and would really appreciate any help on this, or links to online resources.

Thanks