In our company we do defacto 100% VHDL, and we use (mostly) cocotb for verification. We strive to deliver high reliable designs by means of our methodology, style guides, reviews, ci/cd build automation and all. I would say we are very successful with our approach.

However, at times we get into touch with external projects, sometimes ASIC designs, that use UVM (and thus Systemverilog). Since we do not make ASICs ourselves, we don't really know whether UVM is a prerequisite to develop IP for these markets, or whether other methodologies are also common. In other words: do we need UVM per se for building ASIC worthy IP? Is not using UVM a defacto disqualifier?