Hi, so I'm pretty new to Yosys and SymbiYosis, relatively familiar wit SystemVerilog, though I've always used Verilog. I'm trying to run a formal verification on a module (not written by me) written in SystemVerilog.

Here's my sby file:

[options]
mode prove
depth 25

[engines]
smtbmc

[script]read_verilog -sv -formal mymodule.v
prep -top mymodule


[files]
mymodule.v

So, when I run sby -f mymodule.sby I get the following error:

ERROR: syntax error, unexpected OP_CAST

At this line:

    assign noise_pal_lut = '{

For more context:

logic [10:0] noise_pal_lut[16];
    assign noise_pal_lut = '{
        11'h200, 11'h280, 11'h550, 11'h5D5,
        11'h393, 11'h74F, 11'h61B, 11'h41F,
        11'h661, 11'h1C5, 11'h6AE, 11'h093,
        11'h4FE, 11'h12D, 11'h679, 11'h392
    };

As I said, really new to this Yosys world, and couldn't find anything on this on the docu, so I don't know if it's related to Yosys or the SystemVerilog module itself.

Edit: Temporary solution

Replace code block with:

reg [10:0] noise_pal_lut [16];
initial begin
    noise_pal_lut[0] = 11'h200;
    noise_pal_lut[1] = 11'h280;
    noise_pal_lut[2] = 11'h550;
    noise_pal_lut[3] = 11'h5D5;
    noise_pal_lut[4] = 11'h393;
    noise_pal_lut[5] = 11'h74F;
    noise_pal_lut[6] = 11'h61B;
    noise_pal_lut[7] = 11'h41F;
    noise_pal_lut[8] = 11'h661;
    noise_pal_lut[9] = 11'h1C5;
    noise_pal_lut[10] = 11'h6AE;
    noise_pal_lut[11] = 11'h093;
    noise_pal_lut[12] = 11'h4FE;
    noise_pal_lut[13] = 11'h12D;
    noise_pal_lut[14] = 11'h679;
    noise_pal_lut[15] = 11'h392;
end