I've created a project in VHDL using Quartus II and when connected to the FPGA, everything seems to work. We're required to simulate in ModelSim and hand in screen shots of our waveforms. I've written a test bench but can't figure out how to use it to simulate my project. Can anyone offer some insight that I must have missed?

edit: Got it to work. Instead of using the NativeLink settings I created a new project in Modelsim, added my .vho file and my vhdl test bench, compiled them, and simulated the test bench. Not too sure what was going on there at first. I guess I was looking for options that were unavailable thanks to outdated tutorials. Thanks for all the help!